Note: here tab is must otherwise make will present error The general syntax of a Makefile rule is as follows: target: dependency1 dependency2. Now all these steps of compiling & linking are cumbersome if source and header files are increased in number, so we make a single Makefile to compile and generate binary by entering single command i.e. -o is used to link all required the objects and generate single executable file.-c is used to generate object file from source file.-I is used to include the current directory (./) where header file located.
#HOW TO WRITE A MAKEFILE FOR C PROGRAM MANUAL#
The following are the manual steps to compile the project and produce the target gcc -c -I.
#HOW TO WRITE A MAKEFILE FOR C PROGRAM CODE#
function.c function.h and main.c to compile and generate binary, this is the simple way to compile your code rather than write compilation line on terminal again and again. And after the end of this small course you can write and understand Makefile easily.įor example if you have three files. Now writing Makefiles, But before that i want to tell you that i have divided this course in different levels so you can start slow with level 1 and go on. => For a large project, when a few changes are made to the source, manually recompiling the entire project each time is tedious, error-prone and time-consuming. => An important feature is that when a project is recompiled after a few changes, it will recompile only those files which are changed, and any other files that are dependent on it. It can be used to compile whole project in well arranged manner and generate your target according to your make rule(which we will discuss later) by entering single command that is make. => Large projects can contain multiple source files which are dependent in one another or arranged in hierarchical manner for example, in order to compile file A, you have to first compile B in order to compile B, you have to first compile C and so on. In simple words, makefile will compile your source code in simple & fast way. Makefile is a script written in a certain prescribed syntax which helps to build the target output (normally, one or more executables) from source files by compilation and linking.
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